1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including advanced transistor elements that comprise advanced gate structures including a metal-containing electrode and a high-k gate dielectric of increased permittivity.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass products. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide is preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon or other metal-containing materials, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that is accomplished by decreasing the thickness of the silicon dioxide layer. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be restricted to high-speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has, thus, been suggested to replace silicon dioxide with high permittivity materials, such as tantalum oxide (Ta2O5), with a k of approximately 25, strontium titanium oxide (SrTiO3), having a k of approximately 150, hafnium oxide (HfO2), HfSiO, zirconium oxide (ZrO2) and the like.
When advancing to sophisticated gate architecture based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while additionally maintaining leakage currents at an acceptable level. On the other hand, metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Therefore, the threshold voltage of the transistors is significantly affected by the work function of the gate material that is in contact with the gate dielectric material, and an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be guaranteed.
For example, appropriate metal-containing gate electrode materials, such as titanium nitride and the like, may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. For this reason, it has been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material at the interface between the high-k dielectric material and the channel region of the transistor device, in order to appropriately “adapt” the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired low threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique at an early manufacturing stage, which may also represent an additional complex process step, which, however, may avoid complex processes for adjusting the work function and thus the threshold voltages in a very advanced process stage.
It turns out, however, that the manufacturing sequence of forming the threshold adjusting semiconductor alloy may have a significant influence on transistor characteristics, as will be described in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 above which is formed a silicon-based semiconductor material 102 having an appropriate thickness for forming therein and thereabove transistor elements. Furthermore, an isolation structure 102C is formed in the semiconductor layer 102, thereby laterally delineating and thus defining active regions 102A, 102B. In this context, an active region is to be understood as a semiconductor material in which an appropriate dopant profile is formed or is to be created in order to form PN junctions for one or more transistor elements. In the example shown in FIG. 1a, the active region 102A corresponds to a P-channel transistor while the active region 102B represents an N-channel transistor. That is, the active regions 102A, 102B comprise an appropriate basic dopant concentration in order to determine the conductivity of a P-channel transistor and an N-channel transistor, respectively. It should be appreciated that the active regions 102A, 102B may comprise or may receive other components, such as germanium, carbon and the like, in order to appropriately adjust the overall electronic characteristics. Similarly, in the active region 102A, an appropriate valence band offset is to be adjusted with respect to a sophisticated gate electrode structure still to be formed by forming an appropriate semiconductor alloy, as will be described later on.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following conventional process strategies. First, the isolation structure 102C is formed by well-established lithography, etch, deposition, planarization and anneal techniques, in which a trench is formed in the semiconductor layer 102, which is subsequently filled with an appropriate insulating material, such as silicon dioxide and the like. It should be appreciated that the process sequence for forming the isolation structure 102C may result in a more or less pronounced stress level that may be induced in the active regions 102A, 102B, for instance by forming a dense silicon oxide material, at least partially, in the isolation trenches 102C, which may result in a stressed state of a portion of the silicon dioxide material. After removing any excess material and planarizing the surface topography, the further processing is typically continued by performing a plurality of implantation processes using an appropriate masking regime in order to introduce the required dopant species for generating the basic dopant concentration in the active regions 102A, 102B corresponding to the type of transistors to be formed therein and thereabove. After activating the dopant species and re-crystallizing implantation-induced damage, the further processing is continued by exposing the device 100 to an oxidizing ambient 110, which is typically established on the basis of elevated temperatures, for instance in the range of 700-1200° C., and supplying oxygen in order to obtain a desired oxidation rate. Consequently, during the dry oxidation process 110, a mask layer 104 may be formed in a well-controllable manner during the process 110. For instance, a maximum thickness of the mask layer 104 may be 10 nm or less.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which an etch mask 105, such as a resist mask, is formed above the semiconductor device 100 such that the mask material 104 on the first active region 102A is exposed, while the portion of the mask material 104 formed on the second active region 102B is protected by the mask 105. The etch mask 105 may be formed by any well-established lithography techniques. Thereafter, an etch process is applied in order to selectively remove the mask material 104 from the first semiconductor region, which is typically accomplished by using any selective etch chemistry, such as diluted hydrofluoric acid (HF), which enables a selective removal of silicon dioxide material while substantially not attacking silicon material.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage, i.e., after the selective removal of the mask material 104 and the removal of the etch mask 105 (FIG. 1b). It should be appreciated that, due to the preceding etch sequence, a certain material loss may also occur in the isolation structure 102C, i.e., in an exposed portion thereof.
FIG. 1d schematically illustrates the semiconductor device 100 when exposed to a further reactive process ambient 106, which may include a cleaning process and the like in order to prepare the device 100 for the subsequent deposition of a silicon/germanium alloy selectively on the first active region 102A. The process 106 may be established on the basis of any appropriate chemistries in order to remove contaminants and the like, which may have been created during the previous removal of the etch mask and the like. Typically, the cleaning process 106 may cause a certain degree of material erosion of the mask 104, thereby reducing a thickness thereof, as indicated by 104R, however, without intending to expose surface portions of the second active region 102B. It should be appreciated that the cleaning process 106, which may remove native oxides and the like, may be required so as to obtain appropriate surface conditions for epitaxially growing the silicon/germanium material in the subsequent process step. In order to not unduly expose the semiconductor device 100 to any other environmental conditions, such as the clean room atmosphere and the like, typically, a very restricted queue time requirement may have to be respected, i.e., a certain time interval between the cleaning process 106 and the subsequent actual deposition of the silicon/germanium alloy should not be exceeded in view of the process quality of the subsequent deposition process.
FIG. 1e schematically illustrates the semiconductor device 100 during a selective epitaxial growth process 107 in which process parameters, such as temperature, pressure, flow rates of precursor gasses and the like, are appropriately selected such that material deposition may be substantially restricted to exposed silicon surface areas while the dielectric surfaces may substantially prevent a deposition of material. Consequently, during the process 107, a silicon/germanium material 108 may be selectively formed on the active region 102A and to a certain degree on the isolation structure 102C, depending on the degree of exposure of any sidewall surfaces of the active region 102A. As previously explained, the finally obtained threshold of a transistor to be formed in and above the active region 102A may strongly depend on the characteristics of the layer 108, such as the germanium concentration and the thickness thereof, such that precisely determined process conditions have to be established during the process 107 and thus also during the cleaning process 106 and a time interval between these two process steps. It should be appreciated that a further cleaning process may typically be performed prior to actually depositing the material 108, which, however, may also strongly depend on the efficiency of the cleaning process 106. On the other hand, the mask layer 104 is to efficiently prevent material deposition on the active regions 102B in view of transistor characteristics of a corresponding N-channel transistor to be formed in and above the active region 102B.
After the deposition process 107, the mask layer 104 is removed, for instance, by using selective wet chemical etch recipes and thereafter the further processing is continued by forming the actual transistor structures.
FIG. 1f schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which a transistor 150A is formed in and above the active region 102A, including at least a portion of the silicon/germanium alloy 108. Similarly, a transistor 150B is formed in and above the active region 102B, wherein, in the transistor 150B, the presence of a silicon/germanium alloy should be avoided. In the manufacturing stage shown, the transistors 150A, 150B, which represent a P-channel transistor and an N-channel transistor, respectively, comprise a gate electrode structure 160A and 160B, respectively. As shown, the gate electrode structure 160A is formed on the threshold adjusting silicon/germanium alloy 108 and comprises a gate dielectric material 161 comprising a high-k dielectric material, in combination with a metal-containing electrode material 162. Furthermore, a “conventional” electrode material, such as a polysilicon material 163, is typically formed above the electrode material 162. The gate electrode structure 160B has a similar configuration except for the threshold adjusting silicon/germanium alloy so that the gate dielectric material 161 is directly formed on the active region 102B. Furthermore, the transistors 150A, 150B comprise a spacer structure 151, which may have any appropriate configuration in order to obtain a desired dopant profile for drain and source regions 153 and to provide a desired mask for a silicidation process, which may still be performed in a later manufacturing stage. Additionally, a channel region 152 is laterally enclosed by the drain and source regions 153 and connects to the gate dielectric material 161. Thus, in the transistor 150A, the channel region 152 may also comprise a portion of the silicon/germanium alloy 108, thereby providing a desired work function and thus threshold of the transistor 150A.
The semiconductor device 100 as illustrated in FIG. 1f may be formed on the basis of any well-established process techniques, which include the deposition of the materials 161, 162 and 163, possibly in combination with other materials, such as dielectric cap layers, anti-reflective coating (ARC) materials, hard mask materials and the like. It should be appreciated that the materials 161 and 162 may thus be selected such that a desired high capacitive coupling is achieved in combination with a superior conductivity, while also a desired work function and thus threshold for the transistor 150B may be set without requiring any additional band gap adjustments. After the patterning of the sophisticated layer stack in order to obtain the gate electrode structures 160A, 160B, the drain and source regions 153 may be formed on the basis of well-established implantation techniques using appropriate masking regimes. It should be appreciated that additional strain-inducing mechanisms may be implemented, if required. In principle, the transistors 150A, 150B may provide superior performance and may allow the adjustment of the basic transistor characteristics in an early manufacturing stage due to the provision of the silicon/germanium alloy 108 and appropriate metal species in the layer 162, thereby avoiding sophisticated manufacturing techniques in a very advanced manufacturing stage in order to appropriately adjust the threshold voltages of field effect transistors, as may be required in so-called replacement gate approaches. However, it turns out that a certain degree of transistor variability may be observed in the transistor 150B, due to the presence of silicon/germanium residues 108R, which may be created in an early manufacturing stage when forming the silicon/germanium layer 108 (FIG. 1e). For example, the presence of the residues 108R may change the electronic characteristics of the active region 102B and may also have a negative influence during the further processing, for instance when forming metal silicide regions in the drain and source regions 153. On the other hand, a certain degree of transistor variability may also be observed for the P-channel transistor 150A, which may be correlated with the corresponding queue time dependency, as previously explained, in particular when the device 100 may be reworked, for instance subjected to an additional cleaning process due to a queue time violation prior to the deposition of the silicon/germanium layer 108.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.